1. Field of the Invention
This invention relates to a high-frequency switch circuit arrangement and in particular to an art of improving resistance to a surge of a high-frequency switch circuit arrangement.
2. Description of the Related Art
A mobile communication terminal such as a mobile telephone uses GHz-band radio waves at the communication time. At the time, field effect transistors (FETS) using gallium arsenide (GaAs) excellent in high frequency characteristics are used in an antenna switch circuit, a transmission-reception. switch circuit, etc., as switching elements.
FIG. 8 is a circuit diagram to show the configuration of a high-frequency SPDT (Single-Pole Double-Throw) switch using GaAs FETs as switching elements.
The high-frequency SPDT switch has a function of selectively switching the output path of an input high-frequency signal. As shown in the figure, a first signal terminal RF1 is placed on the input side and a second signal terminal RF2 and a third signal terminal RF3 are placed on the output side. The high-frequency signal input through RF1 is output to one of RF2 and RF3 (the switch input/output may be made opposite).
A first field effect transistor stage FET1 of a switch circuit for switching the high-frequency signal path is provided between the first signal terminal (RF1) and the second signal terminal (RF2). Likewise, a second field effect transistor stage FET2 is provided between the first signal terminal (RF1) and the third signal terminal (RF3). (In the description to follow, it is assumed that the field effect transistor stage means a switch circuit using a field effect transistor as a switching element.)
Turning on/off both the field effect transistor stages is controlled by control signal inputs CTL1 and CTL2, whereby the signal terminal RF1 is electrically connected to one of RF2 and RF3.
On the other hand, the FET in the off state is equivalent to capacity component (capacitor) and assuming that the portion between RF1 and RF2 is on and the portion between RF1 and RF3 is off, the high-frequency signal from RF1 leaks to the side of RF3 through the equivalent capacity component when the switching FET2 is off. To draw the signal into ground (GND) with the FET in the on state, a fourth field effect transistor stage FET4 and a capacitative element C1 for cutting DC is placed between the third signal terminal RF3 and the ground terminal GND, forming a shunt circuit 1; likewise, a third field effect transistor stage FET3 and a capacitative element C2 for cutting DC is placed between the second signal terminal RF2 and the ground terminal GND, forming a shunt circuit 2.
The shunt circuit 1, 2 serves a function of short-circuiting the path in an alternating current manner and causing unnecessary high-frequency component to escape to the high-frequency ground (ground potential). Accordingly, the isolation characteristic between the contacts (FR2 and FR3) in the high-frequency switch circuit arrangement is kept good.
A capacitative element always exists in a high-frequency switch circuit arrangement containing a shunt circuit like the high-frequency SPDT switch described above. It is desirable that the capacitative element should be manufactured on a single GaAs chip and be integrated as MMIC (Monolithic Microwave IC) from the viewpoint of reducing the number of external parts.
However, in the MIM (Metal Insulator Metal) capacity manufactured on the GaAs substrate, the insulating film between upper and lower electrodes is very thin and therefore the capacitative element often is at the lowest electrostatic breakdown voltage in the high-frequency switch circuit and needs to be handled with extreme care. That is, the element having the lowest electrostatic breakdown voltage dominates the electrostatic breakdown voltage of the whole high-frequency switch circuit arrangement and therefore it becomes important to improve the electrostatic breakdown voltage of the capacitative element to improve resistance to a surge of the high-frequency switch circuit arrangement.
The simplest method for improving the electrostatic breakdown voltage of the capacitative element as described above is a method of using a high dielectric material for the capacitative element and widening the space between upper and lower electrodes for improving electrostatic resistance of the capacitative element or a method of connecting a protective element in parallel with an element having low electrostatic breakdown voltage (in this case, capacitative element), thereby improving resistance to a surge as the whole high-frequency switch circuit arrangement.
For example, the method of using a high dielectric material for the capacitative element is disclosed in JP-A-10-335582. The method of connecting a protective element in parallel with an element having low electrostatic breakdown voltage is disclosed in JP-A-2003-100893.
However, to use the methods described above, the following problems may occur:
To manufacture an element using a high dielectric material in MMIC, the forming process becomes complicated and the number of masks for capacitative element formation and the total number of steps are increased.
To attempt to create without increasing the number of steps, the high dielectric material is also formed as interlayer dielectric and thus a function problem as interlayer dielectric may occur, namely, an increase in parasitic components may introduce a problem.
On the other hand, in the method of adding a protective diode as a protective element in parallel with a protected element for improving the electrostatic breakdown voltage, it is actually difficult to manufacturer an element as a protective diode namely, a diode having high electrostatic breakdown resistance voltage on the GaAs substrate, and the manufacturing process becomes complicated. Further, connecting a protective diode may lead to addition of parasitic capacity and may cause the high-frequency characteristic to be degraded.